The present invention relates to a method for measuring the physical characteristics of a semiconductor device. The present invention has particular applicability in manufacturing silicon-on-insulator devices.
In conventional silicon-on-insulator (SOI) technology, a metal oxide semiconductor (MOS) device is formed on a substrate comprising a bottom silicon layer, an insulating layer (referred to as a xe2x80x9cBOX layerxe2x80x9d), such as a silicon dioxide layer, on the bottom silicon layer, and an upper silicon layer formed on the BOX layer. The MOS device has a source region and a drain region, separated by a channel region, formed in the upper silicon layer, a gate oxide layer formed on the main surface of the upper silicon layer, and a conductive gate, typically of polysilicon, formed on the gate oxide layer. The source and drain regions are typically formed by ion implantation of impurities, and each have a junction with the upper silicon layer.
The location of the source/drain junctions below the main surface of the upper silicon layer, referred to as the xe2x80x9csource/drain junction depthxe2x80x9d, is important to the characterization of a device. In general, the shallower the junction depth, the better the performance of a device. For example, in SOI technology, the junction depth determines the xe2x80x9cfloating body effectxe2x80x9d of the device, which is an important indicator of how well a device will perform. Therefore, junction depth needs to be monitored for process control and quality control purposes.
Conventional methods for measuring junction depth include spreading resistance profiling (SRP), which determines the electrically active concentration of species forming the source/drain junctions, and secondary ion mass spectroscopy (SIMS), which measures the chemical concentration of a dopant. Disadvantageously, both the SRP and SIMS measurements tend to be inaccurate, especially in the proximity of a silicon/silicon dioxide interface. This is problematic when measuring SOI junction depths, because SOI source/drain junctions typically occur close to the bottom of the upper silicon layer, at or near the interface with the BOX layer. Thus, SRP and SIMS techniques have difficulty correctly locating source/drain junctions in SOI devices.
There exists a need for a methodology for accurately locating source/drain junctions in SOI devices.
An advantage of the present invention is a technique for accurately determining the source/drain junction locations in SOI devices based on measurements of electrical characteristics of the devices.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method for determining a source/drain junction depth of an inspected semiconductor device formed on a substrate, the substrate comprising a bottom semiconductor layer, an insulating layer on the bottom semiconductor layer, and an upper semiconductor layer, the inspected device having a source region and a drain region formed in the upper semiconductor layer, the method comprising measuring a threshold voltage of a bottom transistor comprising the source region, the drain region and the substrate; and determining the source/drain junction depth of the inspected device based on the threshold voltage of the bottom transistor.
Another aspect of the present invention is a method for determining a source/drain junction depth of an inspected semiconductor device formed on a substrate, the substrate comprising a bottom semiconductor layer, an insulating layer on the bottom semiconductor layer, and an upper semiconductor layer, the inspected device having a source region and a drain region formed in the upper semiconductor layer. The method comprises measuring a threshold voltage of a bottom transistor comprising the source region, the drain region and the substrate by grounding the source and applying a low voltage to the drain, and applying a test voltage varing from about zero to at least the threshold voltage, wherein the threshold voltage comprises a voltage that corresponds to formation of a depletion region between the source and drain regions. The threshold voltages of bottom transistors of a plurality of reference devices are also determined, the reference devices each having a different known source/drain junction depth and having physical characteristics corresponding to those of the inspected device; the threshold voltage of the inspected device bottom transistor is compared to the threshold voltages of the reference device bottom transistors; and the source/drain junction depth of the inspected device is determined to be about the same as the source/drain junction depth of one of the reference devices when the threshold voltage of the inspected device bottom transistor is about equal to the threshold voltage of the one of the reference devices bottom transistor.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.